Digital PLL Design
A phase-locked loop or phase lock loop (PLL) is a control system that generates a signal that has a fixed relation to the phase of a “reference” signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. A phase-locked loop is an example of a control system using negative feedback.
In simpler terms, a PLL compares the frequencies of two signals and produces an error signal which is proportional to the difference between the input frequencies. The error signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input. This input is called the reference and is often derived from a crystal oscillator, which is very stable in frequency.
Phase-locked loop. (2009, March 10). In Wikipedia, The Free Encyclopedia. Retrieved 16:40, March 10, 2009, from http://en.wikipedia.org/w/index.php?title=Phase-locked_loop&oldid=276279511
Electrical engineers and hobbyists may want to try this free interactive online tool we found to simplify the designing of digital phase locked loops (PLLs)! http://www-users.cs.york.ac.uk/~fisher/mkpll/
Simply fill in the interactive form and click ‘submit’ to get your PLL designed for you in just seconds.
